This invention relates generally to digital systems and specifically to maintaining clock speeds in the presence of temperature variations.
As modern digital electronic systems become larger and more complex, quality on-chip clock distribution becomes increasingly important. Propagation delays across an integrated circuit""s clock distribution network result in undesirable clock skew, which in turn may adversely impact performance of the integrated circuit. A delay-locked loop (DLL) may be used to compensate for propagation delays across a clock distribution network by sufficiently delaying an input clock signal before applying it to the distribution network so that it is in phase with an output clock signal of the distribution network.
FIG. 1 shows a system 1 having a DLL 10 connected to a clock distribution network 15. DLL 10 includes a programmable delay line 11 and control logic 12. An input clock signal CLK_IN is coupled to input terminals of programmable delay line 11 and control logic 12. Programmable delay line 11 produces a delayed clock signal CLK_OUT, which in turn is coupled as an input clock signal to clock distribution network 15. CLK_OUT is routed across clock distribution network 15, which is tapped at a selected point and provided as a feedback signal CLK_FB to control logic 12. Control logic 12 compares the respective phases of CLK_IN and CLK_FB and, in response thereto, provides a control signal to programmable delay line 11. In response to the control signal provided by control logic 12, programmable delay line 11 delays CLK_IN until CLK_IN is in phase with CLK_OUT, e.g., until their respective rising edges align. Once the clock signals are in phase, the DLL locks, and thereafter maintains CLK_IN and CLK_OUT in phase with each other.
A DLL""s programmable delay line typically includes many individually selectable buffer stages that allow for the delay inserted into a clock signal to be incrementally changed without causing glitches in the clock signal. Buffer stages are typically formed using CMOS inverters. For example, FIG. 2 shows a conventional buffer stage 2 as having two series-connected CMOS inverters coupled between a voltage supply VCC and ground potential. The gate delays of the CMOS inverters provide the incremental delays of the programmable delay line.
The gate delay associated with each buffer stage is dependent upon fabrication process considerations such as, for instance, implant and threshold voltage levels, and thus may change with variations in the fabrication process. Since a delay line typically includes many buffer stages, relatively small changes in the buffer stage gate delay may produce a significant change in the cumulative delay of the delay line, which in turn may result in an undesirable shift in operating frequency. Accordingly, it is desirable to maintain a constant buffer stage gate delay over process variations in order to prevent undesirable shifts in the operating frequency.
The delay of each buffer stage is also dependent upon temperature. As temperature increases, circuit speed decreases, which in turn results in longer (e.g., slower) gate delays for the buffer stage. Conversely, as temperature decreases, circuit speed increases, which in turn results in a shorter (e.g., faster) gate delays. For example, where a buffer stage may provide a 600 picosecond delay at 80xc2x0 Celsius, the same buffer stage may provide a delay of 500 picoseconds at 0xc2x0 Celsius. Thus, in this example, the buffer stage delay is 20% faster at 0xc2x0 Celsius than it is at 80xc2x0 Celsius. The resultant increase in buffer stage gate delay at low temperatures may undesirably increase the minimum operating frequency at which the delay line is able to lock. The resulting shift in minimum operating frequency may preclude synchronization with associated circuits, and thus may violate specified operating parameters.
One solution to maintaining a specified minimum operating frequency at low temperatures is to provide additional buffer stages in the delay line. These additional buffer stages are selected at lower temperatures to increase the total delay along the delay line, and thereby compensate for faster delays associated with low temperatures. Although effective in compensating for faster delays at low temperatures, providing additional buffer stages in a delay line undesirably increases silicon area and manufacturing costs. Thus, it is desirable to maintain delay of the delay line at low temperatures without providing additional delay stages.
A method and apparatus are disclosed that maintain a substantially constant gate delay over a temperature range. In accordance with the present invention, the supply voltage to which a delay circuit""s buffer stages are coupled is adjusted in response to changes in temperature according to a predetermined relationship in order to maintain a substantially constant delay in the delay line over a range of temperatures. Decreasing gate delays of gates in the delay line resulting from decreases in temperature are offset by decreasing the supply voltage, which in turn increases gate delays. Conversely, increasing gate delays resulting from increases in temperature are offset by increasing the supply voltage, which in turn decreases gate delays.
Providing a supply voltage VCC that changes with temperature in accordance with present embodiments is in marked contrast to prior art teachings of maintaining a constant voltage over a temperature range. Indeed, voltage supplies which use bandgap reference circuits to maintain a constant supply voltage over a temperature range are well-known. Here, slowing circuit speed at low temperatures by decreasing the supply voltage, as implemented according to present embodiments, is contrary to the conventional wisdom of increasing operating speeds at low temperatures.
In some embodiments, a control circuit is connected to the reference voltage circuit that supplies VCC to the delay circuit, and adjusts VCC in response to temperature to maintain substantially constant gate delay of gates in a delay line over the temperature range. In one embodiment, the control circuit includes a microprocessor and a look-up table embodying a desired supply voltage versus temperature relationship. In another embodiment, the control circuit is formed as part of an existing bandgap reference circuit associated with the reference voltage circuit, and therefore consumes minimal silicon area.